Technical Field
The invention relates generally to the design of integrated circuits; and, more particularly, it relates to the design of integrated circuits having both fixed logic and programmable logic components.
Related Art
Programmable devices are a class of general-purpose integrated circuits that can be configured for a wide variety of applications. Such programmable devices have two basic versions, mask programmable devices, which are programmed only by the manufacturer, and field programmable devices, which are programmable by the end user. In addition, programmable devices can be further categorized as programmable memory devices or programmable logic devices. Programmable memory devices include programmable read only memory (PROM), erasable programmable read only memory (EPROM) and electronically erasable programmable read only memory (EEPROM). Programmable logic devices include programmable logic array (PLA) devices, programmable array logic (PAL) devices, erasable programmable logic devices (EPLD) devices, and programmable gate arrays (PGA). Field programmable gate arrays (programmable gate array) have become very popular for telecommunication applications, Internet applications, switching applications, routing applications, et cetera.
As is known, programmable gate arrays offer the end user the benefits of custom CMOS VLSI integrated circuits while avoiding the initial cost, design time delay, and inherent risk of Application Specific Integrated Circuits (ASIC). While programmable gate arrays have these advantages, there are some disadvantages. For instance, a programmable gate array programmed to perform a similar function as implemented in an ASIC requires approximately 25 to 50 times more die area than the ASIC. As such, the manufacturing expense of a programmable gate array is greater than that of an ASIC. In addition, a programmable gate array requires significantly more printed circuit board space and consumes more power than an equally functional ASIC. Furthermore, programmable gate arrays are designed to target various implementations and usually do not deliver the performance of the ASICs.
To mitigate some of the disadvantages of programmable gate arrays with respect to ASICS, some programmable gate array manufacturers include ASIC like functions on the same substrate as the programmable logic fabric. For example, programmable gate arrays are now commercially available that include random access memory (RAM) blocks and/or multipliers in the programmable logic fabric. As such, the programmable logic fabric does not have to be programmed to perform RAM functions and/or multiplier functions, when such functions are needed. Thus, for these functions, significantly less die area is needed within the programmable gate array.
While including fixed logic circuits in the programmable gate array fabric offers end users greater programming options with less die area consumption, end users are now demanding greater performance and flexibility from programmable gate arrays. In particular, end users would like to see more fixed logic functionality, (i.e., ASIC like functionality) embedded within the programmable logic fabric of programmable gate arrays, while retaining the versatility of traditional programmable gate arrays. Within embodiments of programmable gate arrays having embedded fixed logic circuitry, given the relative newness of this particular area of art, there is little or no teaching that is directed towards the manner in which the various components of the fixed logic circuits and the programmable circuitry should be laid out within a design.
Further limitations and disadvantages of the manner in which such circuitry is laid out will become apparent to one of skill in the art through comparison of such systems with the invention as set forth in the remainder of the present application with reference to the drawings.
In order to overcome these shortcomings, as well as other shortcomings of the prior art devices, an integrated circuit designed and constructed according to the present invention includes a number of configurable logic blocks arranged into a fabric such that the fabric has an opening therein that is surrounded by configurable logic blocks. Formed within the opening in the fabric is a fixed logic circuit that includes a number of input/output lines and control lines. Surrounding the fixed logic circuit within the opening is interconnecting logic that interfaces the input/output lines and the control lines of the fixed logic circuit to the fabric. According to the present invention, this interconnecting logic distributes the input/output and control lines along a number of configurable logic blocks bordering the opening. The interconnecting logic may include interconnecting tiles that interface directly to the configurable logic blocks of the fabric.
In some embodiments, the input/output lines and control lines of the fixed logic circuit include hundreds of individual lines. However, the opening is bordered by far fewer that this number of configurable logic blocks. Thus, in such case, each of a number of configurable logic blocks bordering the opening services a plurality of address lines, a plurality of data lines, and a plurality of control lines. The interconnecting tiles of the interconnecting logic each terminate a set of address lines, data lines, and control lines of the fixed logic circuit and thus interface the signals to the configurable logic blocks that border the opening.
According to one aspect of the present invention, a group of the lines supporting the fixed logic circuit, e.g., data, address, and control lines of a processor bus, are distributed along a number of interconnecting tiles bordering a first side of the opening. In such embodiments, other lines of the processor are distributed along interconnecting tiles bordering other sides of the opening. Such distribution of the signal lines of the fixed logic circuit allows the fabric to be managed so that differing portions of the fabric are configured to perform differing functions, such functions corresponding to the locally presented inputs/outputs of the fixed logic circuit.
When multiple fixed logic circuits are present, symmetry in the presentation of input/output, control, etc. lines of the fixed logic circuit to the fabric may be employed. For example, in an implementation that includes multiple fixed logic processing cores, symmetry may be employed in the presentation of lines to the fabric about a central portion of the fabric. Such symmetry in presentation of lines to the fabric provides efficiencies in fabric configuration both in cooperative and stand-alone configurations of multiple fixed logic circuit implementations.
Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.